Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JP2575449
Kind Code:
B2
Abstract:
A row address signal (Ai) is supplied to a row address input buffer (13), and a column address signal (Aj) is supplied to a column address input buffer (14). The row address signal (Ai) supplied to the row address input buffer (13) is then supplied to a row main decoder (19), through a row address predecoder (15), the column address signal (Aj) supplied to the column address input buffer (14) being supplied to a column address predecoder (17). An output from the column address predecoder (17) is supplied to a filter or delay circuit (20), and an output signal from the filter or delay circuit (20) is supplied to a column main decoder (21). One memory cell (MC) in a memory cell array is selected in response to decode outputs from the row main decoder (19) and the column main decoder (21), and readout data of the selected memory cell (MC) is amplified by a sense amplifier (24). An output from the sense amplifier (24) is output through a data output circuit (25) and a data output buffer (26). An erroneous detected signal of the column address buffer (14), arising from power supply noise generated when an output from the data output buffer (26) is inverted, is eliminated or reduced by the filter or delay circuit (20).
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Inventors:
OOTANI TAKAYUKI
MATSUI MASAKI
MATSUI MASAKI
Application Number:
JP3561488A
Publication Date:
January 22, 1997
Filing Date:
February 18, 1988
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G11C11/41; G11C5/14; G11C8/18; G11C11/413; H01L27/10; (IPC1-7): G11C11/41; G11C11/413
Domestic Patent References:
| JP5954093A | ||||
| JP60254488A |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)