Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2648840
Kind Code:
B2
Abstract:
A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.
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Inventors:
MATSUO AKINORI
WATANABE MASARU
WADA MASASHI
WADA TAKESHI
NAKAMURA YASUHIRO
WATANABE MASARU
WADA MASASHI
WADA TAKESHI
NAKAMURA YASUHIRO
Application Number:
JP29517288A
Publication Date:
September 03, 1997
Filing Date:
November 22, 1988
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
HITACHI CHO ERU ESU AI ENJINIARINGU KK
HITACHI CHO ERU ESU AI ENJINIARINGU KK
International Classes:
G06F12/16; G11C16/02; G11C16/06; G11C16/10; G11C16/34; G11C17/00; G11C29/00; G11C29/02; G11C29/04; G11C29/12; G11C29/46; G11C29/48; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/06
Domestic Patent References:
| JP1154398A | ||||
| JP1137495A | ||||
| JP6252798A | ||||
| JP61294565A |
Attorney, Agent or Firm:
Tokuwaka Mitsumasa