PURPOSE: To obtain an electric equipment having clock signal sources of dual configuration in which clock signal sources for O and 1 systems and the clock supply from a signal source of other system is maintained even when one signal source is faulty.
CONSTITUTION: Suppose that a 0 system clock signal source 1a is faulty during normal operation and an H level is being outputted to an FF circuit means 3b and an AND circuit means 4b of a 1 system. Since an L level is being outputted from a *Q terminal of the 1 system FF circuit means 3b, the means 4b keeps outputting an L level to a 1 system clock signal source 1b. The 1 system signal source 1b is normally operated by the input of the L level. Furthermore, when the 0 system clock signal source 1a is faulty and an L level is being outputted to the FF circuit means 3b and the AND circuit means 4b of the 1 system, an H level is being outputted from the *Q terminal of the 1 system FF circuit means 3b. Since the means 4b receives the L level input from the 0 system clock signal source 1a, the L level is being outputted to the 1 system clock signal source 1b, which is operated normally.
MINAMIGUCHI HIDENORI
YOSHIDA MITSUNOBU
