Title:
【発明の名称】段数可変m系列符号発生器
Document Type and Number:
Japanese Patent JP3097081
Kind Code:
B2
Abstract:
PURPOSE:To generate (m) series codes of arbitrary number of stages and to simplify a circuit and its control by setting feedback tap information on a feedback tap pattern holding register. CONSTITUTION:The feedback tap pattern holding register 11, a shift register 12, a gate 14 which takes the AND of the bits at positions corresponding to the registers 11 and 12, and a gate 15 which takes the exclusive OR of the output of the gate 14 and sets it as the (m) series code and is set as input to the shift register 12 are provided. And a register 13 which holds a desired mask pattern by performing the logical operation of the output of the feedback tap pattern holding register 11 is provided. Also, a gate 17 which takes the OR of the bits at the positions corresponding to the shift register 12 and the mask pattern register 13, respectively, and a gate 18 which takes the NAND of the output of the gate 17 and outputs an epoch signal are provided. Then, the (m) series codes of arbitrary number of stages can be generated by setting the feedback tap information on the register 11. Thereby, the circuit and its control can be simplified.
Inventors:
Kenji Okamura
Shinobu Ikeda
Shinobu Ikeda
Application Number:
JP13611389A
Publication Date:
October 10, 2000
Filing Date:
May 31, 1989
Export Citation:
Assignee:
NEC
International Classes:
H03K3/84; G06F7/58; (IPC1-7): H03K3/84
Attorney, Agent or Firm:
Umeo Yamauchi