Title:
【発明の名称】重み付き加算回路
Document Type and Number:
Japanese Patent JP2985999
Kind Code:
B2
Abstract:
A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP1 to serially connected first and second inverters INV1 and INV2, and includes grounded weighted capacitances C32 and C11, capacitance C21 connecting the first and the second inverters INV1 and INV2, and a capacitive coupling CP1 such that the closed loop gains of the first and second inverters INV1 and INV2 are substantially equal. The closed loop gains of the first and second inverters INV1 and INV2 are balanced.
More Like This:
| JPS584484 | ADDING AMPLIFIER |
Inventors:
KOTOBUKI KOKURYO
YO KOREYASU
TAKATORI SUNAO
YAMAMOTO MAKOTO
YO KOREYASU
TAKATORI SUNAO
YAMAMOTO MAKOTO
Application Number:
JP4042493A
Publication Date:
December 06, 1999
Filing Date:
February 04, 1993
Export Citation:
Assignee:
TAKATORI IKUEIKAI KK
SHAAPU KK
SHAAPU KK
International Classes:
G06G7/14; (IPC1-7): G06G7/14
Other References:
【文献】永田穣著、「IC演算増幅器とその応用」日刊工業新聞社発行、昭和53年1月30日,P11-P17
【文献】岡村みち夫著、[OPアンプ回路の設計」、CQ出版、1990年9月30日発行、P53-P60
【文献】岡村みち夫著、[OPアンプ回路の設計」、CQ出版、1990年9月30日発行、P53-P60
Attorney, Agent or Firm:
Yamamoto Makoto