Title:
MEMORY CHIP ADDRESS UNIT
Document Type and Number:
Japanese Patent JPS6015688
Kind Code:
A
Abstract:
The memory system writes both horizontal and vertical lines into a two-dimensional array by a mapping process for storing the array in 64K memory chips, with required data transformations, address calculations, and chip hardware. The mapping and hardware provide bit addressability in both horizontal and vertical directions.
Inventors:
DANIERU ROORENSU OSUTAPUKO
Application Number:
JP5129584A
Publication Date:
January 26, 1985
Filing Date:
March 19, 1984
Export Citation:
Assignee:
IBM
International Classes:
G09G5/00; G06F12/00; G06F12/02; G06F12/06; G11C8/00; (IPC1-7): G09G1/02; G11C7/00
Domestic Patent References:
| JPS56118145A | 1981-09-17 | |||
| JPS5784486A | 1982-05-26 |
Attorney, Agent or Firm:
Jiro Yamamoto