Title:
【発明の名称】並列バスシステムを備えたデータ伝送装置
Document Type and Number:
Japanese Patent JP2660980
Kind Code:
B2
Abstract:
PCT No. PCT/DE93/01037 Sec. 371 Date May 4, 1995 Sec. 102(e) Date May 4, 1995 PCT Filed Oct. 29, 1993 PCT Pub. No. WO94/10631 PCT Pub. Date May 11, 1994A configuration for data transfer with a parallel bus system including an address bus, a data bus and a control bus and with several units interfacing with them. A first control line is used to send an acknowledge signal with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line is used to detect addressing errors and accesses to non-existing units and to carry a signal ready control signal to the first unit from the others indicating whether one of the interfaced units was addressed. To do so, the signal ready control signal has dominant and recessive states. During an access cycle, only addressed units generate a dominant state. The control signal is also used for synchronous multipoint access. The invention can be used in bus systems.
More Like This:
| JP4522730 | Subordinate device and provisioning support method |
| JP6948303 | Storage system |
| WO/2000/010095 | STRIPING PACKETS OF DATA ACROSS MULTIPLE VIRTUAL CHANNELS |
Inventors:
ABERUTO MIHIAERU
BUROTSUKU JIIKUFURIITO
BOOTSUENHARUTO YOHANESU
RAIGUSUNERINGU FURANTSU
PUFUATSUTAIHIAA UERUNAA
SHEEUE FURANTSUUKUREMENSU
BUROTSUKU JIIKUFURIITO
BOOTSUENHARUTO YOHANESU
RAIGUSUNERINGU FURANTSU
PUFUATSUTAIHIAA UERUNAA
SHEEUE FURANTSUUKUREMENSU
Application Number:
JP51056094A
Publication Date:
October 08, 1997
Filing Date:
October 29, 1993
Export Citation:
Assignee:
JIIMENSU AG
International Classes:
G06F13/14; G06F13/368; G06F13/378; G06F13/42; (IPC1-7): G06F13/42; G06F13/14
Domestic Patent References:
| JP314060A | ||||
| JP608941A |
Attorney, Agent or Firm:
Tomimura Kiyoshi