Title:
【発明の名称】集積可能な評価回路
Document Type and Number:
Japanese Patent JP2666184
Kind Code:
B2
Abstract:
An integrable evaluating circuit includes a trigger circuit, a first and a second circuit node, both of which serve both as inputs and as mutually-complementary outputs for the trigger circuit, a pair of signal lines exhibiting the same potential in a rest state, switching transistors each being connected between a respective one of the two circuit nodes and a respective signal line of the pair of signal lines, and a signal-enhancement circuit connected between the trigger circuit and the pair of signal lines. A signal occurring on a given one of the two signal lines is initially connected with its signal deviation to the circuit node connected to the given signal line. The switching transistor connected to the given one of the two signal lines is then blocked and cuts off the signal from the circuit node connected to the given signal line. The signal-enhancement circuit then increases the potential at the circuit node connected to the given signal line by a given amount while simultaneously reducing the potential at the other of the two circuit nodes as a result of potential shift. The potential of the circuit node connected to the given signal line is reduced and the potential of the other of the two circuit nodes is increased if the signal has a negative signal deviation.
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Inventors:
Liner, Claus
Application Number:
JP18211487A
Publication Date:
October 22, 1997
Filing Date:
July 21, 1987
Export Citation:
Assignee:
Siemens, Actien Gezershaft
International Classes:
G11C7/06; G11C11/419; H01L21/8242; G11C11/409; H01L27/10; H01L27/108; H03K5/02; (IPC1-7): G11C11/409; G11C11/419; H01L27/10
Domestic Patent References:
| JP5425641A |
Attorney, Agent or Firm:
Tomimura Kiyoshi