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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5835971
Kind Code:
A
Abstract:

PURPOSE: To reduce the space of base-emitter electrode windows by forming wiring contacting with the P base layer on an N type Si collector layer by poly Si, coating the surface with SiO2 and stacking metallic wiring contacting with an N emitter layer.

CONSTITUTION: The N collector layer 23 on an N+ buried collector is isolated by a P+ layer 26, the surface is coated with a poly Si thin layer 27, Si3N4 30a, 30b is formed to the base-emitter electrode window sections, and a P external base 31 and SiO2 32 are shaped through the implantation of B ions and heat treatment. The mask 30a is removed, poly Si 34 is stacked, B ions are implanted, a P+ base connecting layer 35 is molded through heat treatment, the layer 34 is patterned and heated, and SiO2 36 is formed onto poly Si wiring 34'. The mask 30b is removed, a P internal base 37 is shaped through the implantation of B ions and thermal diffusion, an N+ emitter 37 is molded through the implantation of Al ions, and an Al electrode 39 is attached. According to this constitution, the emitter wiring 39 can be overlapped to the base electric wire 34' through the SiO2 36, and 2∼3μm width is sufficient as both electrode windows.


Inventors:
HATAISHI OSAMU
Application Number:
JP13515581A
Publication Date:
March 02, 1983
Filing Date:
August 28, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/73; H01L21/331; H01L29/72; (IPC1-7): H01L29/08
Domestic Patent References:
JPS5544715A1980-03-29
JPS5685860A1981-07-13
JPS5339061A1978-04-10
Attorney, Agent or Firm:
Sadaichi Igita