PURPOSE: To obtain a delay time longer than the repeating time of an input pulse without using a large number of bits for a counter, by reading the writing memory number which is written in a storage device after a time equivalent to the delay time set number.

CONSTITUTION: If an input pulse Pi is applied to an input terminal 8 at a certain time point, a writing memory counter 17 calculates the number D1 of clock pulses Pc for a period d1 from the initiation A of a cycle between cycles A and B of a dividing pulse Pb obtained when the pulse Pi is applied through a time point when the pulse Pi is supplied. Then the fine delay time set number Tm given from a delay time setting part 11 is added to the number D1 to deliver the writing memory number (Tm+D1). Then the writing memory number (Tm+ D1) is written in an address of an RAM 12 equivalent to the sum of the reading address number AR and the rough delay time set number TS during a cycle between B and C of the pulse Pb. The number (Tm+D1) is read out with a delay Ts and then the number (Tm+D1) is subtracted by a pulse Pc, and a pulse Pd is delivered when 0 is obtained from the subtraction.