Title:
ADDRESS DISPLAY CIRCUIT OF TAPE RECORDER
Document Type and Number:
Japanese Patent JPS6047288
Kind Code:
A
Abstract:
PURPOSE:To decrease a display error by applying a binary/BCD conversion whose error is corrected as to and upper bit corresponding to the display digit of a binary address and obtaining a time pulse corresponding accurately to the minimum unit of display by other means after said value is set so as to count the pulse. CONSTITUTION:An address signal is serial/parallel converted by a converting circuit 2. An address detecting circuit 9 detects a synchronous pattern, then outputs one pulse shown in Fig. (b). The binary code data subject to the serial/parallel conversion is converted into a BCD code by a binary/BCD converting circuit 3 comprising ROMs. In case of 23-bit binary code, the conversion is conducted only the upper 13-bit. A counter 6 acts like a counter in the unit of 1sec. A serial adder 7 adds ''1'' always to an input data. A comparator 8 compares data strings in Fig. (a) and (d), and a pulse (e) is outputted only with address jump. The signal (e) is fed to the load terminal of a BCD counter 4 via an OR gate 10 and a new address ''m'' is set.
Inventors:
TSUJI SHIROU
Application Number:
JP15658183A
Publication Date:
March 14, 1985
Filing Date:
August 26, 1983
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11B27/28; G11B27/34; (IPC1-7): G11B27/28; G11B27/34
Attorney, Agent or Firm:
Toshio Nakao
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