Title:
【発明の名称】静電放電現象によるJFETの損傷を減少するための手段
Document Type and Number:
Japanese Patent JPH03503944
Kind Code:
A
Abstract:
Differentially-connected pairs of JFETs on an IC chip are protected from ESD events by connecting respective discharge control resistors to the drains of the JFETs in such a manner as to be in series with any flow of current through either JFET.
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Inventors:
Wolf, Edward, El
Application Number:
JP50480489A
Publication Date:
August 29, 1991
Filing Date:
April 14, 1989
Export Citation:
Assignee:
ANALOG DEVICES,INCORPORATED
International Classes:
H01L29/812; H01L21/338; H01L27/02; H03F1/52; H03F3/45; (IPC1-7): H01L21/338; H01L29/812; H03F1/52; H03F3/45
Attorney, Agent or Firm:
Shuta Sekine