PURPOSE: To obtain withstand voltage of an element isolation region for isolating between memory cell transistor arrays and to reduce an area of the element by lowering a voltage to be applied to a control gate of a memory cell transistor selected at the time of writing.

CONSTITUTION: The method for writing a memory cell 1 of a NAND type nonvolatile memory comprises the steps of applying a voltage of a first polarity (e.g. positive) to a control gate 15a of a selected memory cell transistor 11a, applying a voltage of a second polarity (e.g. negative) to control gates 15b, 15c, 15d of non-selected memory cell transistors 11b, 11c, 11d, and applying a voltage of the second polarity (e.g. negative) to a bit line 17. Or, the transistor is written by the steps of implanting electrons in all the transistors, then applying a negative voltage to a control gate of the selected transistor, and selectively extracting the electrons.