Title:
MULTIPROCESSOR TRANSFER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6073777
Kind Code:
A
Abstract:
PURPOSE:To obtain standardization of a transfer system and cost reduction of the system construction by providing a processor with a command branch table, a neighboring-station information table, a table information table and other related tables and assembling these into the same transfer program. CONSTITUTION:Processors 1-1-1-6 have respective independent memory spaces, and have connecting relations which are indicated by 1-7-1-11. When data transfer between main memories of respective processors is executed, universal data transfer control can be executed by incorporating the following tables: A command branch information table which indicates, when data are transferred between main memory units of various processors, the logical bonding relation between the same transfer program, which governs respective data transfer to these processors, these processors and other processors, a table information table, which includes the information of the area accessible from other processors to this processor, a neighboring-station information table which indicates the physical connective relation between this processor and the neighboring processor, and other related tables.
Inventors:
AOKI RIYOUJIROU
IGAWA JIYUICHI
IGAWA JIYUICHI
Application Number:
JP18341083A
Publication Date:
April 25, 1985
Filing Date:
September 29, 1983
Export Citation:
Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F13/14; G06F15/16; G06F15/177; G06F15/80; (IPC1-7): G06F13/14; G06F15/16
Domestic Patent References:
| JPS5933958A | 1984-02-24 |
Attorney, Agent or Firm:
Kazuhide Okada