Title:
TEST INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS59128464
Kind Code:
A
Abstract:
PURPOSE: To enable the formation of a plurality of testing inputs from one testing input terminal, by handling the output signal of a shift register as testing input.
CONSTITUTION: High or low level data is applied to a testing input terminal 12 and a reset input terminal 4 is changed from a low level to a high level while the data is written in the shift register 13 and this operation is repeated to write the data in the entire stages of the shift register 13. This written data outputted from each stage of the register 13 and the output signal is utilized as testing input to form a plurality of test modes.
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Inventors:
YAMASHITA HIROYUKI
Application Number:
JP384283A
Publication Date:
July 24, 1984
Filing Date:
January 13, 1983
Export Citation:
Assignee:
SUWA SEIKOSHA KK
International Classes:
G01R31/3185; H01L21/66; G01R31/28; H01L21/822; H01L27/04; (IPC1-7): G01R31/28; H01L21/66
Attorney, Agent or Firm:
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