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Title:
FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS6028275
Kind Code:
A
Abstract:

PURPOSE: To enable to sufficiently reduce the series resistance between gate and source and the capacitance between gate and source by a method wherein a recess structure is formed in such a manner that the source side will have forward taper form and the drain side will have inverted taper form.

CONSTITUTION: An aperture is provided on the expected region 7 of a GaAs wafer 5 where a gate electrode will be formed using photoresist 6. Then, a dry etching is performed on the wafer 5. At this time, the wafer is inclinably positioned so that the GaAs etching makes progress with a tapered angle. Besides, the etching is performed using the etchant which is the mixture of phosphoric acid and hydrogen peroxide, and the desired recessed structure is formed. Subsequently, Al 8 is coated on the whole surface as a gate metal, and a gate 9 is formed by removing unnecessary metal. Then, a drain electrode 10 is formed on the inverted taper side and a source electrode 11 is formed on the forward taper side respectively. The GaAs FET manufactured as above has sufficiently small gate-source series resistance and gate-drain capacitance, thereby enabling to obtain excellent high frequency characteristics.


Inventors:
ISHIUCHI HIROAKI
Application Number:
JP13702583A
Publication Date:
February 13, 1985
Filing Date:
July 27, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/812; H01L21/338; H01L29/417; H01L29/80; (IPC1-7): H01L21/28
Attorney, Agent or Firm:
Uchihara Shin