PURPOSE: To improve the gate sensitivity and the high voltage withstanding property of the titled TRIAC when a remote gate is used and the device is operated in trigger mode by a method wherein a stepped difference part is provided at the point directly below a gate located on the junction face which crosses in common the p-n-p-n structure region and the n-p-n-p region of the TRIAC.
CONSTITUTION: A silicon substrate 1 constitutes an n type base layer. The first region of p type base (pB1) layer 2 and the second region of p type base (pB2) layer 2 are formed on the main surface of the substrate 1, and then the first region of n type emitter (nE1) layer 4 and an n type gate layer 6 are formed thereon. On the other hand, the second region of p type base (pB2) layer 3 and the first region of p type emitter (pE1) layer are formed on the other surface of the substrate 1, and the second region n type emitter (nE2) layer 5 is formed thereon. As a stepped difference part is provided at the point located directly below the gate on the base layer (nB) which crosses in common an n-p-n-p region and a p-n-p-n region, the effective thickness of the base layer at the part directly below the gate can be thinned off.
JPS57196569A | 1982-12-02 | |||
JPS568876A | 1981-01-29 | |||
JPS55124262A | 1980-09-25 |