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Title:
MOS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6062159
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of floating effect of a semiconductor layer as well as to improve the characteristics of the titled semiconductor device by a method wherein, when the semiconductor device is three-dimentionally formed by providing a P-channel MOS type transistor and an N-channel MOS type transistor, the source potential of the N-channel transistor to be positioned on the upper part and the semiconductor layer including said N-channel transistor are brought in the same potential.

CONSTITUTION: A thick field oxide film 33 is formed on the circumferential part of an N type semiconductor substrate 30, a gate electrode 35 is provided in the center part on the surface of the substrate 30 surrounded by the film 33 through the intermediary of a thin gate oxide film 34, a P+ type source region 31 and a drain region 32 are formed on the surface layer part of the substrate 30 located on both sides of the gate electrode 35, and a P-channel MOS type transistor A is formed. Then, a P type semiconductor layer 37 to be used for an N-channel MOS type transistor B is deposited on the electrode 35 through the intermediary of a gate insulating film 36, and an N+ type source region 38 and a drain region 39 are formed thereon. At this time, a P+ type region 40 is formed by diffusion in the layer 37, the regions 38 and 40 are shortcircuited by a source electrode 43c and they are brought to the same potential.


Inventors:
NAKAHARA MORIYA
Application Number:
JP16988283A
Publication Date:
April 10, 1985
Filing Date:
September 14, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L27/00; H01L21/02; H01L27/12; H01L29/78; H01L29/786; (IPC1-7): H01L27/00; H01L27/12
Attorney, Agent or Firm:
Takehiko Suzue