Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6098663
Kind Code:
A
Abstract:
PURPOSE: To prevent the reduction of the effective area of a capacitor constituting a memory cell by a method wherein memory cells adjacent to each other are electrically isolated by a P-N junction in the title dynamic device of two-element type.
CONSTITUTION: In said device in which the memory cell is composed of a MOS transistor and a capacitor, two N type regions 8 and 8 are electrically isolated by the P-N junction between the N type region one electrode of the memory cell and a P type region 19 of a low specific resistance. Such a construction prevents the reduction of the effective area of the capacitor constituting the memory cell by the isolating region.
Inventors:
SHIMOTORI KAZUHIRO
OZAKI HIDEYUKI
FUJISHIMA KAZUYASU
MIYATAKE HIDEJI
OZAKI HIDEYUKI
FUJISHIMA KAZUYASU
MIYATAKE HIDEJI
Application Number:
JP20695683A
Publication Date:
June 01, 1985
Filing Date:
November 02, 1983
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C11/401; H01L21/8242; H01L27/10; H01L27/108; H01L29/78; (IPC1-7): G11C11/34; H01L27/10; H01L29/78
Attorney, Agent or Firm:
Masuo Oiwa