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Title:
SYNCHRONIZING CIRCUIT OF VITERBI DECODER
Document Type and Number:
Japanese Patent JPS5912649
Kind Code:
A
Abstract:

PURPOSE: To attain the word synchronism by a viterbi decoder itself, by obtaining a carrier phase large in a metric increment for eliminating the uncertainty of the carrier phase.

CONSTITUTION: A metric increment operating circuit 20 discriminates a maximum metric value from a new metric value selected at a branch selecting circuit 203 when the synchronism is started, and a subtractor 22 calculates a difference with the maximum metric being 1 time slot before stored in a register 23 is calculated. Since this value becomes the increment of the maximum metric, the synchronism/asynchronism is discriminated with a threshold value circuit 40 by outputting this value to an integrator 30. The output phase of a phase shifter 10 is changed with this discriminating signal.


Inventors:
YASUDA YUTAKA
HIRATA YASUO
FURUYA YUKITSUNA
MURAKAMI SHIYUUJI
NAKAMURA KATSUHIRO
Application Number:
JP12094382A
Publication Date:
January 23, 1984
Filing Date:
July 12, 1982
Export Citation:
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Assignee:
KOKUSAI DENSHIN DENWA CO LTD
NIPPON ELECTRIC CO
International Classes:
H04L7/00; H03M13/23; H04L1/00; (IPC1-7): H04L1/10; H04L7/00
Attorney, Agent or Firm:
Uchihara Shin



 
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