Title:
MASKED PROGRAMMABLE LOGIC ARRAY
Document Type and Number:
Japanese Patent JPS60103644
Kind Code:
A
Abstract:
PURPOSE:To contrive to improve the integration degree and the operating speed by a method wherein logical element blocks connected so as to construct required logical circuits and wiring channels for their mutual wiring are provided. CONSTITUTION:The titled array is constructed by including four logical element blocks 13 and 14 arranged in array form and connected so as to construct respective required logical circuits and the wiring channels 11 for the mutual wiring of the blocks. Here, the block 13 and 14 are made up of AND gate elements and OR gate elements, respectively; and constitute unit PLA's together with input registers 12 and output registers 15. The blocks alter the connection by the process of metal wiring by changing masks, thus altering the logical formula as the PLA. Besides, the switching of input signals and output signals from the wiring channels to each of the unit PLA's is performed by the process of metal wiring in the same manner.
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Inventors:
KITAMURA YOSHINARI
Application Number:
JP21178583A
Publication Date:
June 07, 1985
Filing Date:
November 11, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/112; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)