PURPOSE: To perform tests and analyses with a memory under a condition where the memory is used for its own purpose by adding the memory in which a test program is stored to a microcomputer bus in a control device.
CONSTITUTION: The address allocation of memories 2, 3, 18, and 24 is performed in such a way that areas A and B are controlled by the memories 2 and 3 and both of the memories 2 and 3 have the same area as the memory 18 has. Moreover, the use of either one of the memories 2 and 3 is selected by a memory access inhibit signal MINH. When the memories 18 and 24 are used as memories after a testing device 1A is packaged, a control signal generating circuit 20 reset a microprocessor 6 through a signal line 11 and loads a test program into the memory 18 through a peripheral control circuit 21. When the circuit 20 puts a memory selection inhibit signal SINH on a signal lien 9 and an address decoder 4 outputs the memory selection inhibit signal MINH to signal lines 5A and 5B thereafter, access to the memories 2 and 3 is inhibited and the circuit 20 is released from the reset condition. Then the microprocessor 6 operates in accordance with the test program of the memory 18 and the result is outputted through the control circuit 21.
MIZOKAWA SADAO
KAWAKAMI MASAYUKI
| JPS53105148A | 1978-09-13 | |||
| JPS54142040A | 1979-11-05 |