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Title:
ERROR CORRECTING DEVICE
Document Type and Number:
Japanese Patent JPS6146625
Kind Code:
A
Abstract:

PURPOSE: To improve the error correcting capability and to prevent erroneous correction by discriminating the reliability at decoding (error correction) of the 1st stage depending on the result of error detection of digital demodulation.

CONSTITUTION: A digital demodulation circuit applies EFM digital demodulation of a data series and also applies error detection, generates a pointer PD at each symbol, the 1st decoder 44 decodes a C1 code from reception data and the pointer, the pointer PD as to the corrected symbol is cleared and the 2nd decoder 42 decodes the C2 code. Then the pointer PD is given to the 1st decoder 44 to check the number of the pointer PD and the presence of an error position calculated with the pointer PD at decoding to prevent erroneous correction at C1 decoding, the number of symbols clearing the pointer is increased and the number of symbols to be corrected at the C2 decoding of the next stage is increased.


Inventors:
SAKO YOUICHIROU
Application Number:
JP16849884A
Publication Date:
March 06, 1986
Filing Date:
August 10, 1984
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11B20/18; H03M13/27; (IPC1-7): G11B20/18; H03M13/22
Domestic Patent References:
JPS58173933A1983-10-12
Attorney, Agent or Firm:
Masatomo Sugiura



 
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