PURPOSE: To diagnose an error detection and correction circuit at memory accesing of 1/m-word and to improve the resolution of error, by providing a check bit in the memory data unit of 1/n-word.

CONSTITUTION: A memory array 21 stores the high-order 1/2-word among memory data when n=2, and a memory array 22 stores similarly the low-order 1/2- word. The check bit C is added to the memory data of each 1/2-word. Error detection and correction ECC circuits 31, 32 perform error detection based on the inputted 1/2-word and the check bit C for attaining error correction. In case of the readout of 1/m-word, the desired bit is inputted to both the ECC circuits 31, 32 with the control of a memory controller 30. A comparison circuit COMP33 compares signals outputted from the ECC circuits 31, 32 and detects coincidence/ dissidence.