Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TRANSISTOR OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPS60182215
Kind Code:
A
Abstract:

PURPOSE: To generate an output potential which is at a sufficient level and resistant to the variation of a manufacture process by increasing an input potential of an MOS transistor (TR) operated in outputting a power potential level.

CONSTITUTION: When an activated signal 1 goes from a low level to a high level with a signal ' at a high level (power voltage VCC and with an input I', e.g., between inputs I and I' at a low level, nodes N1, N2 start transition to a high level. The node N2 restores immediately to a low level because an MOS TRQ22 is conductive. On the other hand, the node N1 progresses a low level state of the high level node N2 and a TRQ11 is made nonconductive. Then the signal VN1 of the node N1 charges a node N1'. The signal VN1 becomes an input of a bootstrap circuit B1 at the same time and a signal VN9 of high level is generated at a node N9. The signal VN9 increase the potential at the node N1' to a voltage level high than the VCC via a capacitor C2. Thus, the level at an output OUT becomes a level nearly equal to the voltage VCC.


Inventors:
ISHIMOTO SHIYOUJI
TSUJIMOTO AKIRA
Application Number:
JP3800484A
Publication Date:
September 17, 1985
Filing Date:
February 29, 1984
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/417; G11C11/34; H03K5/02; H03K6/02; (IPC1-7): G11C11/34; H03K6/02
Domestic Patent References:
JPS5869113A1983-04-25
JPS5881325A1983-05-16
JPS58147883A1983-09-02
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
Previous Patent: JPS60182214

Next Patent: TRANSISTOR CIRCUIT