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Patent Searching and Data


Title:
DATA PROCESSOR
Document Type and Number:
Japanese Patent JPS5856046
Kind Code:
A
Abstract:

PURPOSE: To diagnose a fault of a shift bus in every circuit block unit, by providing each circuit block with a shift bus input switching circuit, and disconnecting a mode setting register from the shift bus during fault-position bracketing operation.

CONSTITUTION: When a fault is detected over buses 201W208 and the fault position is bracketed by circuit blocksIand II, bits (a) and (b) of a mode setting register 1 are set to logic 1. Then, a mode switching signal 103 is given logic 1 to close NAND circuits 32 and 33, stopping the supply of a clock signal 102 to the register 1. The output 104 of an NAND circuit 31 has logic 1 to signify an AND circuit 35, and the value logic 1 of the bit (b) is transferred to switch a shift bus input switching circuit 2, thereby supplying a shift-in signal 201 through every shift bus of the block II. Further, an NAND circuit 36 closes an NAND circuit 38, so the supply of a shift-out signal 202 in every shift bus unit of the blockIis cut off, thereby disconnecting the register 1 from the shift buses.


Inventors:
WATANABE YASUHISA
Application Number:
JP15580081A
Publication Date:
April 02, 1983
Filing Date:
September 29, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F11/22; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Toshi Inoguchi



 
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