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Patent Searching and Data


Title:
OPERATION PROCESSING DEVICE
Document Type and Number:
Japanese Patent JPS5814251
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for a circuit forming a special constant for the execution of rounding operation, by providing a partial reset control circuit forming a reset signal to an upper-order m-bit of a register to be the input of an operation circuit.

CONSTITUTION: An operation processing device consists of a data input terminal 1, registers 2' and 3 of n-bit length each, an operation circuit 4 inputting the registers 2' and 3, an output switching circuit 5, a data output terminal 6, a control circuit 7', and a partial reset control circuit 9 generating a partial reset signal 10. When the instruction of rounding operation of the (m+1)th or lower bits is given from the control circuit 7' to the operand in n-bit length started from the head 1st bit, the circuit 9 transmits the partial reset signal from the head 1st bit of the register 2' to the m-th bit.


Inventors:
SATOU YOUICHI
Application Number:
JP11196981A
Publication Date:
January 27, 1983
Filing Date:
July 17, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F7/38; G06F7/48; G06F7/499; (IPC1-7): G06F7/38
Attorney, Agent or Firm:
Uchihara Shin