Title:
DIGITAL SIGNAL REPRODUCER
Document Type and Number:
Japanese Patent JPS5934796
Kind Code:
A
Abstract:
PURPOSE: To reduce a converting clock frequency, by applying the converting processing of PWM after the bit of a PCM digital signal is split.
CONSTITUTION: The bit of the PCM digital signal 1 are split into, e.g., two, and the result is converted into a PWM signal at separate PCM-PWM converters 2, 3. Thus, the clock frequency is reduced extremely in comparison with the clock frequency not split. Further, the PWM signal obtained from the said converters 2, 3 is amplified at switching amplifier sections 4, 5 with required weighting, they are applied to voice coils 7, 8 wound independently as a speaker drive signal.
Inventors:
NURIYA KOUZOU
Application Number:
JP14500782A
Publication Date:
February 25, 1984
Filing Date:
August 20, 1982
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03M1/82; H04R1/00; H04R3/00; (IPC1-7): H03K13/20; H04R3/00
Domestic Patent References:
JPS51123546A | 1976-10-28 | |||
JPS49126248A | 1974-12-03 |
Attorney, Agent or Firm:
Akira Kobiji (2 outside)