Title:
DEMODULATING CIRCUIT
Document Type and Number:
Japanese Patent JPS60666
Kind Code:
A
Abstract:
PURPOSE:To correct earlier the word shift of a demodulation circuit caused by an error by detecting plural specific patterns from a signal train after DELTA/6 conversion so as to take the synchronism of the demodulation circuit. CONSTITUTION:An ROM 18 outputs a 4-bit data word corresponding to a 6-bit code word in the order of P4, P3, P2 and P1, and ''0'' is outputted from a P0 when a 6-bit input is coincident with a pattern represented by a code word and ''1'' is outputted when a dissident data is inputted, and a counter 21 is counted up when an error is produced at the reading of a reproducing signal and an erroneous code word is inputted. When a code word is shifted in a 12-bit shift register 10 and a specific pattern ''110010100101'' is detected at gates 12-17, a counter 24 is cleared so as to work in synchronism with the code word. In this case, the number of times of dissident patterns is counted by the counter 21 by an output from the P0 of the ROM 18 and a gate 20 of a CLR signal of the counter 24 is closed only when the count value exceeds a prescribed value. Thus, if the word synchronism with the code word is locked it is restored quickly in this way.
Inventors:
ITOU MASAHIRO
KIMURA HIROYUKI
KIMURA HIROYUKI
Application Number:
JP10588383A
Publication Date:
January 05, 1985
Filing Date:
June 15, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11B20/14; (IPC1-7): G11B20/14
Attorney, Agent or Firm:
Akio Takahashi
Next Patent: JPS60667