Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TESTER FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS601578
Kind Code:
A
Abstract:

PURPOSE: To test an integrated circuit easily and quickly with free control of the weight or the like of a test pattern by controlling a random number distribution converter for controlling the random number responding to a random number generator with an external binary digit.

CONSTITUTION: The distribution of a uniform random number of a fundamental input from a uniform random number generator 10 is controlled with a random number distribution converter 12 according to binary digits α and β from an external unit 11. With the value α, the right and left movement of the probability distribution varies with a conversion function unit 13 of an equipment 12 to determine the right and left balance with respect to the weight center while with the value β, the geometry of the distribution changes through a conversion function unit 14 to control the ratio of magnitude between the center peak of the probability distribution and both ends thereof. A test pattern is outputted from a test pattern generator 15 responding to the equipment 12 to test a 2 input AND gate with the probability of 3/4 for the appearance of 0, for instance, by a pattern of the corresponding appearance probability thereby enable the testing of an integrated circuit easily and quickly.


Inventors:
TATEISHI AKIMITSU
Application Number:
JP10919983A
Publication Date:
January 07, 1985
Filing Date:
June 20, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA KK
International Classes:
G01R31/3183; G01R31/319; G01R31/28; H01L21/66; (IPC1-7): G01R31/28; H01L21/66
Attorney, Agent or Firm:
Hideaki Togawa