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Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS59105351
Kind Code:
A
Abstract:

PURPOSE: To contrive to improve the integration degree by enabling to reduce the area which condensers of the same capacitance occupy by a method wherein the process of oxidation to form a surface oxide film is added in the process of forming a MISFET.

CONSTITUTION: P- type wells 10 and 13 are respectively formed on one main surface of an N type Si substrate 11. A field SiO2 film 9 which isolates the MISFET part 14 from the capacitance element part 15 is formed, and further gate oxide films 5 and 21 are grown on the well. A poly Si gate electrode 17 and a poly Si layer 2 are formed on the gate oxide film of each part into a fixed pattern. With the poly Si gate electrode 17 as a mask, an N+ type source region and a drain region 19 are formed respectively on both sides thereof. A phosphorus glass film 6 is adhered, the part on the capacitance element thereof is removed by photoetching, and the surface of the poly Si layer 2 exposed to this removed region 20 is lightly oxidized, resulting in the growth of an SiO2 film 4. Each aluminum electrode 27, 28, 1, 3, and 29 is formed respectively by patterning aluminum adhered over the entire surface.


Inventors:
TAKANASHI AKIRA
Application Number:
JP21389982A
Publication Date:
June 18, 1984
Filing Date:
December 08, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/04; H01L21/822; H01L29/78; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Toshiyuki Usuda



 
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