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Patent Searching and Data


Title:
CACHE BUFFER CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS595482
Kind Code:
A
Abstract:

PURPOSE: To reduce page out processing between a main internal memory and an external memory, by storing rewritten part in a cache buffer without performing page rewriting of main internal memory at the time of cache rewriting.

CONSTITUTION: When data processing in a central processing unit CPU 0 or CPU 1, if data of a local storage buffer 3-0 or 3-1 are rewritten, corresponding data of global storage buffer 5 of memory control unit 4 are rewritten simultaneously. The rewritten data are controlled by a main memory control section 6, and data correction due to rewriting caused by purging of data of the buffer 5 is not made for main internal memories MSU0WMSU2. Rewritten part is stored in a cache buffer CSBM of a changed storage cache buffer memory unit 10. Accordingly, page out processing between the main internal memory and external memory is reduced, and instantaneous allotment of real page can be dealt with immediately.


Inventors:
SAKAMOTO YOSHINORI
Application Number:
JP11357882A
Publication Date:
January 12, 1984
Filing Date:
June 30, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/08; (IPC1-7): G06F13/00
Attorney, Agent or Firm:
Akira Yamatani