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Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JPS5839123
Kind Code:
A
Abstract:

PURPOSE: To make it difficult that the circuit is affected by noises, by controlling an up/down counter by the output signal, which is obtained by comparing the phase of the output signal of a programmable divider with that of a reference frequency, to change an electrostatic capacity digitally.

CONSTITUTION: The phase of an output signal fv of a programmable divider 3-1 is compared with a reference frequency fr in a phase comparing circuit part 3-2, and an UP/DOWN signal is generated by the output signal to set an up/down counter 3-9 to the up count mode or the down count mode. A clock signal CK is generated by the output signal obtained in the phase comparison of the phase comparing circuit part 3-2 and is supplied to the up/down counter 3-9. Plural electrostatic capacities in a digital VCO 3-10 are switched digitally by the output signal of the up/down counter 3-9 to control the oscillation frequency.


Inventors:
ICHIDA KENJI
Application Number:
JP13743681A
Publication Date:
March 07, 1983
Filing Date:
September 01, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03L7/18; H03L7/08; (IPC1-7): H03L7/18
Attorney, Agent or Firm:
Uchihara Shin



 
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