PURPOSE: To delay signals similarly, and to prevent the generation of a whisker and malfunction by inserting dummy capacitance using the same P-N junction to another signal line to be synchronized when parasitic capacitance by a tunnel resistor for one cross wiring in a signal line group to be synchronized enters therein.
CONSTITUTION: Wirings 70 and 72, 74 must be crossed on a pattern layout, the tunnel resistor 51 to which an N type region 7-1 is formed is formed in a P type region 6, the wiring 70 is divided into 70-1, 70-2 and connected by the tunnel resistor 51, and the wirings 72, 74 pass on the region 7-1 through an insulating film. A wiring 76 must be synchronized with the wiring 70, a region 7-2 of the same width and length as the region 7-1 is formed in order to give dummy capacitance, and the wiring 76 is divided into two of 76-1 and 76-2 and connected by the region 7-2. The capacitance values and resistance values of the regions 7-1, 7-2 are approximately equal to each other because the regions 7-1, 7-2 have the same width and length and are arranged adjacently. Accordingly, retardation time at points P, Q between the two lines 70, 76 is made approximately constant.
JP2008066797 | OUTPUT DRIVER AND INTEGRATED CIRCUIT DEVICE |
JPS6387736 | SEMICONDUCTOR DEVICE |
JP6656968 | Semiconductor device with ESD protection element |