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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5969954
Kind Code:
A
Abstract:

PURPOSE: To delay signals similarly, and to prevent the generation of a whisker and malfunction by inserting dummy capacitance using the same P-N junction to another signal line to be synchronized when parasitic capacitance by a tunnel resistor for one cross wiring in a signal line group to be synchronized enters therein.

CONSTITUTION: Wirings 70 and 72, 74 must be crossed on a pattern layout, the tunnel resistor 51 to which an N type region 7-1 is formed is formed in a P type region 6, the wiring 70 is divided into 70-1, 70-2 and connected by the tunnel resistor 51, and the wirings 72, 74 pass on the region 7-1 through an insulating film. A wiring 76 must be synchronized with the wiring 70, a region 7-2 of the same width and length as the region 7-1 is formed in order to give dummy capacitance, and the wiring 76 is divided into two of 76-1 and 76-2 and connected by the region 7-2. The capacitance values and resistance values of the regions 7-1, 7-2 are approximately equal to each other because the regions 7-1, 7-2 have the same width and length and are arranged adjacently. Accordingly, retardation time at points P, Q between the two lines 70, 76 is made approximately constant.


Inventors:
FUSE MAMORU
Application Number:
JP18024182A
Publication Date:
April 20, 1984
Filing Date:
October 14, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/04; H01L21/3205; H01L21/768; H01L21/822; H01L21/8226; H01L23/52; H01L23/522; H01L23/535; H01L27/082; (IPC1-7): H01L21/88; H01L27/04; H01L27/08
Attorney, Agent or Firm:
Uchihara Shin