PURPOSE: To reduce the time required for many number of times of test-and- branch and to quicken the operation, by supplying a branched address responding and coping with an input of a discrimination condition signal as a part of control input to a sequencer.

CONSTITUTION: A mapping ROM7 is enabled with a MAP signal outputted from a pipeline register 3, and an address to be branched is determined with the combination of the discriminating condition signal at a point of time and supplied to the sequencer 2. When the instruction is fetched in advance and all interruption signals are not existing, the address is branched to a prescribed address of an interpreter section, and the processing corresponding to the content of the decoded instruction is attained. Further, the advance fetch signal of the next instruction is outputted from an optional step of branching during execution and the advance fetch is attained immediately. In the final step of the instruction executing section, the MAP signal is outputted continuously to enable the ROM7.