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Patent Searching and Data


Title:
MANUFACTURE OF PIN GRID ARRAY
Document Type and Number:
Japanese Patent JPH04111433
Kind Code:
A
Abstract:

PURPOSE: To prevent misregistration, to enable repair by exchange of an IC chip by removing and to enable easy and highly reliable manufacture by arranging a bare chip formed to TAB on an adhesive layer applied to a specified surface of a substrate and by including a process to temporarily fixing it by the adhesive layer.

CONSTITUTION: A conductive adhesive layer 2 is applied and formed on a die pad 1a whereon an IC chip of a substrate 1 with multiple pins is mounted. Thereafter, a bare chip 3 which is formed of a required IC chip formed to TAB is registered and arranged, and temporarily fixed by the adhesive layer 2. Each I/O lead 3a of the bare chip 3 is bonded successively with a corresponding pad 1b of a surface of the substrate 1 for electrical connection in the state. At this time, specified electrical inspection is carried out. Since the bare chip 3 is temporarily fixed, it is possible to attain required electrical connection readily without causing misregistration, etc. Furthermore, when functional trouble is detected in the bare chip 3, removal and exchange, etc., can be realized readily. When functional defect is not detected in the bare chip 3, the conductive adhesive layer 2 is thermally cured.


Inventors:
HIRAI HIROYUKI
NEMOTO TOSHIYA
Application Number:
JP22978190A
Publication Date:
April 13, 1992
Filing Date:
August 31, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/50; H01L23/12; (IPC1-7): H01L21/50
Attorney, Agent or Firm:
Saichi Suyama