PURPOSE: To enable to constitute the capacitance of a pull-up capacitor in the smallest possible area for the titled memory storage by a method wherein the pull-up capacitor is formed by a second polycrystlalline silicon layer and a third layer of polycrystalline layer, which was provided through the intermediary of an insulating film located on the second polycrystalline silicon layer.

CONSTITUTION: When a third polycrystalline layer is used for a digit line, the polycrystalline layer is not at all superposed on a second polycrystalline silicon layer, which constitutes the gate of a field-effect transistor on a memory cell part, or even when there exists superposition, it can be made small, and, therefore, it is unnecessary to thicken an interlayer oxide film more than the thickness which is required to maintain withstand voltage. Similarly, as the third polycrystalline silicon layer can be grown after an impurity diffusion layer has been formed, the structure indicated by region IV can be obtained, and as the oxide film located between the impurity diffuion layer and the third polycrystal line silicon layer is formed in the thickness required to prevent the under layer from etching when a dry-ething is performed on the third polycrystalline silicon layer, the film thickness can be made as thin as possible which withstand voltage permits.