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Title:
TRANSISTOR
Document Type and Number:
Japanese Patent JPS5753977
Kind Code:
A
Abstract:

PURPOSE: To enhance collector-base capability of withstanding reverse voltages by a method wherein an electrically conductive gate layer is formed under a collector layer and is connected to an emitter layer.

CONSTITUTION: An N epitaxial layer 12 and SiO2 13 are placed in piles on a P type Si substrate 11. An island type layer 12 separated by a P layer 14 is provided with a P base 15. Located in the P base 15 is an N emitter 16 that is provided with electrodes 17, 18, and 19. The base electrode 18 extends over the edge of the collector- base junction onto the collector, when caution is to be used so that the electrode 18 may not yield at a point on the collector-base junction edge. Then the emitter 16 and the substrate 11 are connected with each other. Collector 12 dopant concentration and thickness as well as gate layer 11 dopant concentration are properly selected so that the two depletion layers in collector-base and collector-gate junctions may communicate to each other before field strength therein reaches a critical value when a reverse bias is applied to the collector-base junction. By this, the capability for withstanding higher collector-base reverse voltages can be greatly improved without adjusting base diffusion depth or collector dopant concentration.


Inventors:
HOSOI TAMIKAZU
Application Number:
JP12978380A
Publication Date:
March 31, 1982
Filing Date:
September 17, 1980
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L29/73; H01L21/331; H01L29/06; H01L29/72; (IPC1-7): H01L29/08
Domestic Patent References:
JPS54109780A1979-08-28