Title:
TRANSLINEAR MULTIPLIER
Document Type and Number:
Japanese Patent JP3171137
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a perfect four-quadrant multiplier to be linearly operated corresponding to two input voltages by providing a multiplier core circuit which is composed of a nonuple tail cell with the output of a linear gain cell group as an input and outputs the multiplied value of two signals.
SOLUTION: Concerning the respective differential outputs of two voltage/ current converting circuits 101 and 102 to which a 1st input signal voltage Vx and a 2nd input signal voltage Vy are respectively inputted, two stages of diodes 104 and 105 and diodes 106 and 107 are defined as loads, and differential voltages 2ΔVx and 2ΔVy are respectively outputted between the terminals of these diodes. These differential voltages 2 Vx and 2 Vy are passed through differential amplifiers 108 and 109 of a gain '1', and the desired sum voltage or difference voltage of differential voltages 2ΔVx and 2ΔVy is outputted by plural linear gain cell groups 103 defined as differential inputs, and supplied as the respective base voltages of nine transistors at the bipolar nonuple tail cells consisting of the multiplier core circuit.
Inventors:
Katsuji Kimura
Application Number:
JP11041197A
Publication Date:
May 28, 2001
Filing Date:
April 11, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06G7/163; H03F3/45; H03G11/08; (IPC1-7): G06G7/163; H03F3/45; H03G11/08
Domestic Patent References:
| JP9298423A | ||||
| JP9102005A | ||||
| JP8315055A |
Attorney, Agent or Firm:
Asamichi Kato