PURPOSE: To control each processor easily with less hardware, by using one receiving data line and transmitting data line as a common line and one control output line and control input line each for a characteristic line to each subordinate processor.
CONSTITUTION: To the transmission and reception control part 10 of a main processor 9, a transmitting signal line (SoD), a receiving signal line (SiD), and control output lines (RQT1, RQT2∼RQTk) and control input lines (IRQ1, IRQ2∼IRk) for respective subordinate processors 14, 15 and 16 are connected. When data is transmitted from the control part 10, the control part 10 sends a request-to-send signal to a party side via the RQTi and, once a permit-to-send signal is sent back from the party side via the IRQi, transmits data through the SoD. When the processing is to be interrupted at the party side during the transmission processing, the SiD is set to an "H". When the control part 10 generates interruption processing with higher priority, the transmission processing is interrupted.
MIYAGAWA KATSUHIKO
HIROZAWA KAZUTOYO
HASEGAWA SHIYOUROU
| JPS5466043A | 1979-05-28 | |||
| JPS54152827A | 1979-12-01 |