PURPOSE: To simplify the constitution of this system by predetermining a flip- flop applying speed conversion processing at every apeed of a transmission line of a transmission data and switching a data write clock to a speed conversion elastic memory in response to the speed and selecting and outputting the data from the flip-flop used for the speed conversion processing.

CONSTITUTION: Switching means 3,4 are changed over in response to the speed of the transmission line of a transmission data to implment speed conversion processing by a switching signal in the interface system for a transmission line for a multiplex conversion and a prescribed data write clock is given from the means 3 to a speed conversion elastic memory 1, in which the transmission data is written. Then the means 4 connects FF(1-1)-(1-n) decided in advance and a line termination processing circuit 2 in response to the speed of the transmission line and a data read clock from the circuit 2 is used to send the data of the relevant FF to the read circuit 2. Thus, the transmission data subjected to speed conversion is outputted from the circuit 2 as a serial data and the speed conversion processing for plural systems is implemented by one system.