Title:
TREE CIRCUIT
Document Type and Number:
Japanese Patent JP3652447
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the parallelism of circuit operation and to speed up a multiplier.
SOLUTION: Three four-input two-output addition blocks 2a to 2c and one extensive four-input two-output addition block 1a are arranged on the 1st step of the tree circuit. Two four-input two-output addition blocks 2d, 2e are arranged on the 2nd step and a four-input two-output addition block 2f is arranged on the 3rd step. The number of logical steps in the critical pass of the tree circuit is reduced by matching the arrival time of input signals to respective addition blocks on the same step.
Inventors:
Yoshiki Tsujihashi
Application Number:
JP19492096A
Publication Date:
May 25, 2005
Filing Date:
July 24, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F7/509; G06F7/52; G06F7/53; G06F7/533; (IPC1-7): G06F7/52; G06F7/50
Domestic Patent References:
| JP62022146A | ||||
| JP4216125A | ||||
| JP6168100A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita
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