To provide the trellis encoder for a TV signal where a frequency base component is accurately generated and maintained.

A data stream is given to a buffer 52 and a staging/timer circuit 54, where the data stream is correctly arranged based on the residue. The data are fed to a nibble selection circuit 56 at a proper timing, and a 2-bit nibble selected properly is coded by a trellis encoder 58. An output of the trellis encoder is fed to a multiplexer 59 where the data, synchronization bits and a pseudo random number are multiplexed, and an output of the multiplexer is fed to an output register. Since an output of a symbol counter 53 and a segment counter 55 whose reset is controlled by a control logic 51 is given to an enabler 57 that gives an enable signal to other circuit corresponding to the frame processing of the data, each element needing a position of the input data in a frame acquires the data.