Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TWO-SIDE SIMULTANEOUS LAPPING METHOD FOR GAAS WAFER
Document Type and Number:
Japanese Patent JPS62120973
Kind Code:
A
Abstract:

PURPOSE: To provide easier manufacture of GaAs wafer with precision and less amount of warp by mixing a grinding liquid incl. abrasive grains for lapping with an etching liquid having effect to dissolve GaAs chemically between the upper and lower surface reference boards.

CONSTITUTION: Each GaAs wafer is nipped by an upper and a lower surface reference board for lapping which operate at different revolving speeds, and both sides of the ware are lapped simultaneously. The processing distortion layer generated at the surface of the GaAs wafer in the course of said lapping operation is dissolved by the etching liquid contained in the grinding liquid while it serves grinding with abrasive grains contained therein, and then is removed to relieve stresses at the surface of wafer, which should contribute to reduction of a warp otherwise generated there. At this time, the ratio of the mechanical grinding speed by the abrasive grains for lapping to the chemical dissolution speed by etching liquid shall preferably the approximately ten to one.


Inventors:
AKIYAMA HIROKI
TOYOSHIMA TOSHIYA
TAKAHASHI AKITETSU
Application Number:
JP26066985A
Publication Date:
June 02, 1987
Filing Date:
November 20, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI CABLE
International Classes:
B24B37/00; H01L21/304; (IPC1-7): B24B37/00; H01L21/304
Attorney, Agent or Firm:
Toshiyuki Usuda



 
Previous Patent: JPS62120972

Next Patent: JPS62120974