PURPOSE: To suppress the reduction in the AD conversion precision by specifying the arrangement of plural comparators so as to use one comparator by two low-order comparator groups alternately.

CONSTITUTION: Clock wires CLK1A, CLK1A, CLK2A, CLK2A, for a loworder comparator group A and clock wires CLK1B, CLK1B, CLK2B, CLK2B, for a low-order comparator group B are extended in a 1st direction and comparators being components of the comparator groups A, B are arranged alternately in the upper and lower directions. Furthermore, a relative distance between the comparators belonging to the low-order comparator group A and the clock wires CLK1A, CLK1A, CLK2A, CLK2A, for the low-order comparator group A and a relative distance between the comparators belonging to the low-order comparator group B and the clock wires CLK1B, CLK1B, CLK2B, CLK2B for the low-order comparator group B are arranged equally to be deviated alternately in a 2nd direction.