PURPOSE: To make the entire circuit configuration of a unique word detecting circuit simple and small in size, by providing a subtractor which subtracts the output of a counter-adder circuit from the bit number of unique words between the counter-adder circuit and a comparator.

CONSTITUTION: A received data string 1 is impressed upon a shift register 3 by an n-bit amount from a certain bit and detection of the data is started. The data is compared with the parallel output of the register 3 at a dissidence detecting circuit 5. The output number of the circuit 5 is counted and added by means of a counter- adder circuit 7 and the count value is compared with the value of a floating value setting circuit 9 at a comparator 11. When the count value is smaller than the floating value, the data is judged as a proper unique word and an output 'UW' is obtained. Moreover, the output value of the counter circuit 7 is subtracted from the set value of a unique word bit value setting circuit 15 by means of a subtractor 16. The calculated results of the subtractor 16 are a value indicating that how many pieces of bits out of the bit number of the unique word coincide properly and, when the value is larger than the value (unique word bit number - floating value) of a floating value setting circuit 10, it can be judged that the fetched pulse string of the n-bit shift register 3 is an inverted unique word.