PURPOSE: To reduce the number of elements per unit stage by constituting the unit stage of two state holding means and three switching means.

CONSTITUTION: A bistable circuit 50 which is capable of holding its output state is constituted, through a period keeping the H level of a clock signal supplied to a clock signal input terminal 6 by an invertor 11 and a three-state invertor 12. The output of the invertor 11 is supplied to the output terminal 101 of a unit stage 100, and also supplied to the invertor 14 through the three-state invertor 13. The output of this invertor 14 is supplied to the circuit 50 through a bidirectional switch 15, and also supplied to an NAND gate 19 through the bidirectional switch 16 or an invertor 17 and the bidirectional switch 18. A clock signal is supplied through the invertor 21 to the other input terminal of this gate 19, and its output is supplied as a clock signal to the following stage 200. When this counter is constituted of a C-MOS, 26 elements are used per unit stage to reduce the number of elements remarkably.