Title:
VARIABLE LENGTH CODE DECODING CIRCUIT
Document Type and Number:
Japanese Patent JP3113765
Kind Code:
B2
Abstract:
PURPOSE: To reduce the cost of a variable length code decoding circuit by reducing the scale of a data expansion/conversion table and then reducing the memory capacity.
CONSTITUTION: A variable length code decoding circuit decodes the variable length codes of 1 to 2n bit lengths and contains a table 1 which stores in order the least code lengths of the variable length codes and 2m-1 pieces of comparators 4 (m=1, 2...). In such a constitution, 2m-1 pieces of elements are read out of the table at a time and each comparator 4 compares these elements with input of the variable length codes by n/m times to detect the i-th table element. This table element can satisfy the conditions, i.e., 'i-th table element ≤variable length code input <(i+1)-th table element'. Thus the length of the head code of the variable length code input is calculated.
Inventors:
Komagata Yoshinobu
Application Number:
JP25088693A
Publication Date:
December 04, 2000
Filing Date:
October 07, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03M7/42; (IPC1-7): H03M7/42
Domestic Patent References:
| JP5152973A | ||||
| JP595292A | ||||
| JP5235781A |
Attorney, Agent or Firm:
Gunichiro Ariga