PURPOSE: To convert a variable-length code into a fixed-length one by self-synchronization by detecting boundaries between variable-length codes in reception, by making each variable-length code has the same bit as the 1st and last bits and no bit of the same kind as the 1st and last bits as other bits.
CONSTITUTION: A variable-length code consisting of eight bits at a maximum is inputted to a shift register successively as input data and when contents 00 of bits b0 and b1 are set in sections 3-7 and 3-8 of the register 3, a detecting circuit 4 for boundaries between variable-length codes sends it output to a register 5. Then, the data 0 in the section 3-7 of the register 3 is transferred to the register 5, and an ROM for variable-length/fixed-length code conversion outputs a fixed-length code 0000 which corresponds to a [0]. The register 5 sends an ineffective signal to the register 3 to make the data in the section 3-7 ineffective. As the next data, bits b2∼b8 are inputted to the register 3 and when a bit b9 is inputted, the circuit 4 generates an output and a fixed-length code is outputted similarly.
MATSUDA KIICHI
HIRAOKA MAKOTO
HONMA TOSHIHIRO
FUKUDA YUTAKA
