PURPOSE: To minimize a power speed product by providing a high-speed potential supply circuit and a low-speed potential supply circuit in a decoding circuit and selectively switching the high-speed potential supply circuit or the low-speed potential supply circuit by a signal which controls a clock varying circuit.

CONSTITUTION: A clock varying circuit DIV outputs a signal having the same frequency as a clock input signal 0 inputted to an input terminal I to an output terminal when a clock speed switching signal HS is in level '1', but this circuit DIV outputs a signal having a half frequency of said clock input signal 0 to the output terminal O when the signal HS is in level '0'. A precharge circuit is selected when the signal HS is in level '0', but a bias circuit is selected when the signal HS is in level '1'. Consequently, a decoding circuit of low speed and low power consumption is selected when a clock signal CLK is slow, but a decoding circuit of high speed and high power consumption is selected when the clock signal CLK is quick. Thus, the power speed product is minimized.